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RTL Design Engineer (SDC Constraints)
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We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints. The ideal candidate will have deep expertise in RTL design, timing constraints, and close collaboration with synthesis and STA teams.
Design and develop RTL (Verilog/SystemVerilog) for complex ASIC blocks and subsystems
Create, review, and maintain SDC constraints (clock definitions, I/O constraints, false paths, multicycle paths, exceptions, etc.)
Work closely with synthesis, STA, physical design, and verification teams to achieve timing closure
Perform RTL quality checks, linting, and CDC analysis
Support timing debugging and constraint optimization across multiple design iterations
Participate in architecture discussions and design reviews
Ensure deliverables meet performance, power, and area (PPA) goals.
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7+ years of hands-on experience in RTL ASIC design
Strong and mandatory expertise in SDC
Clocking strategies
Timing exceptions
Constraint validation and debug
Proficiency in Verilog/SystemVerilog
Solid understanding of ASIC design flow (RTL Synthesis STA P&R)
Experience working with Synopsys tools (DC, PrimeTime – preferred)
Strong knowledge of timing concepts and timing closure
Excellent debugging and problem-solving skills
Experience in low-power design techniques
Exposure to CDC/RDC methodologies
Experience with complex SoC designs
Scripting knowledge (Tcl / Perl / Python)
Prior experience working with global or distributed teams
Job ID: 144751025
Skills:
Verilog, CDC tools, Axi, APB, AMBA protocols, AHB, systemverilog
Skills:
Area and power-efficient complex RTL design, High performance low latency high bandwidth design techniques, Low power microarchitecture techniques, Experience with simulators and waveform debug tools, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications
Skills:
pipelining , Debugging, Perl, Verilog, Python, Tcl, Analytical Skills, Reset architecture, Clock domain crossing CDC, Micro-Architecture, Linting, Digital Design Fundamentals, systemverilog, FSM design, Synthesis, RTL quality checks, RTL Coding, Low-power design methodologies, ASIC SOC design, Timing Concepts
Skills:
Spi, Uart, Verilog, Arm, System Verilog, I2c, Gpio, USB standards, Synopsys, ASIC design flow, Interconnect fabrics, Arteris fabrics, RTL Coding, Cadence, Scripting in Perl, Peripheral interface IPs, QSPI, I3C, System Verilog assertions, NoC architecture, Third-party IP integration, Axi
Skills:
Uart, Spi, Gpio, Verilog, I2c, Arm, System Verilog, ASIC design flow, Interconnect fabrics, Cadence, Peripheral interface IPs, Arteris fabrics, System Verilog assertions, Axi, Scripting in Perl, APB, RTL Coding, Third-party IP integration, QSPI, I3C, Synopsys, USB standards, NoC architecture
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