Area and power-efficient complex RTL design, High performance low latency high bandwidth design techniques, Low power microarchitecture techniques, Experience with simulators and waveform debug tools, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications

hardware engineering , Verilog, System Verilog, Computer system architecture, low power microarchitecture techniques, SOC DFT, NoC Design, waveform debugging tools, logic design principles, Simulators, high performance design techniques, PD teams, Performance Bandwidth Latency and Bus transactions, AI ML systems

Verilog, ASIC RTL, ECO flows, systemverilog, Low-power design, Synthesis constraints, Micro-architecture, Architecture, Dft, AMBA protocols, Clock reset expertise

Uart, Spi, Verilog, I2c, LINT, cdc, MAS development, Sub-system design, SoC integration, ip design, Quality check flows, AMBA bus protocols, Axi, APB, RTL Coding, Medium complexity protocol, AHB, Microarchitecture

Asic, Rtl Design, cdc, LINT