R&D Engineering, Sr Staff Engineer Design Verification

1. 3+ years of work experience in EDA, preferably in logic optimization and logic synthesis.

2. Strong software skills: minimum 5 years of coding experience in C++.

3. Proficiency in data structures and algorithms.

4. Strong analytical and problem-solving skills.

5. Good understanding of chip design flow.

6. Must be a team player, clear in written and oral communication skills and open to work with diverse teams across multiple time zones.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.