This is your role
- Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis
- Collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution.
- Work with design community in solving critical designs problems to achieve desired performance, area and power targets.
- Deployment of Synthesis solution with various customers working on cutting edge technologies (7nm and forward).
- Develop & deploy training and technical support to customers using Siemens EDA tools.
We don't need superheroes, just superminds!
- Typically requires minimum of 10+ years of experience in Logic Synthesis flows
- Proficiency in Verilog, System Verilog & VHDL.
- Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design & implementation.
- Prior experience in IC digital design flows and front-end EDAT tools including Synthesis, DFT, Formal Verification, Logic Equivalence Checks
- Hands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must.
- Experience with advance technology nodes 7nm and below.
- Hands-on experience in debug & deliver solutions to critical design issues related to synthesis.
- TCL, Perl or Python scripting is a plus.
- Self-motivated team player with a zeal to drive high team performance.
- Good problem solving and debugging skills.
- Strong verbal & written communication skills
