Principal/Senior Principal Verification Engineer

Cadence Bangalore and NOIDA is hiring for ASIC Verification

We are looking for IP Verification Engineers. Join us to work on cutting edge Technology in Semiconductor space.

Position Description:

Design Verification role for IP development team.

B. Tech/M.Tech with 8 to 18 + years of relevant experience.

Position is based in Bangalore/Noida, part of Cadence IP Group.-> Preferred location is Bangalore.

Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI)

UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.

In addition to UVM functional verification, role could involve Formal verification of complex design modules.

In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs.

Understand design and produce detailed verification strategy and test plan.

Self-starter and learner with passion for getting the job done on time with great quality.

Strong problem solving, analytical and debug skills

Excellent verbal and written communications skills

Clearly communicate project status, issues etc.