Principal RTL Integration Engineer - High-Speed SoC / Chiplets

Senior RTL Integration Engineer (High-Speed SoC / Chiplets)

Experience

816 years | SoC / Subsystem Integration / High-Speed Interfaces

Role Summary

We are looking for a senior RTL Integration Engineer to integrate and deliver complex SoC and chiplet subsystems involving high-speed interfaces such as PCIe, Ethernet, DDR, and SerDes. The role requires close collaboration with architecture, DV, analog/SerDes, firmware, and physical design teams in a fast-moving, execution-focused environment.

Key Responsibilities

Integrate complex RTL subsystems and IPs into SoC / chiplet top level

Work with high-speed interfaces:

PCIe (Gen4/5/6)

Ethernet (100G / 200G / 224G multi-rate)

DDR4 / DDR5

Integrate third-party IPs (Synopsys / Cadence / in-house)

Handle clocking, reset, power domains, and interconnects

Resolve integration issues across RTL, DV, and PD teams

Support SoC bring-up and debug at RTL and gate level

Work with global teams (Europe / US)

Must-Have Skills

Strong SystemVerilog / Verilog RTL skills

Proven experience in SoC or chiplet RTL integration

Solid understanding of:

Clock/reset architecture

Power domains (UPF/CPF awareness)

Interconnects (AXI/NoC)

Experience integrating high-speed protocol IPs