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Position: Principal Product Engineer
Grade: T4
Location: Bangalore
Experience: 7-10 Yrs
Job Description
This position presents an exciting opportunity within Cadence's Digital and Signoff Group (DSG) for a Product Engineer. In this dynamic environment, you'll collaborate closely with R&D, Application Engineering & product marketing teams to help drive the development of advanced chip design software tools. Your responsibilities will include:
Provide place-and-route expertise to both Cadence customers and internal development teams
PPA benchmarking on customer and foundry test cases
Evaluate impact of new features on PPA
Be a liaison for new features between customer/foundry and R&D development teams
Develop point solutions with scripting
Data mining and analysis to uncover PPA limiting issues and identify optimization opportunities
Minimum Qualifications:
A Bachelor or Master's degree in EE/CS or equivalent major (Masters level preferred)
A minimum of 7 years of hands on experience with any industry standard place-and-route tools (5 years with Master Degree)
A good understanding of the RTL-GDSII flow
A good understanding of the PDK and DK collaterals
Firm understanding of Timing and power analysis
Good scripting skills
Cadence is a health technology company helping the nation’s most patient-centric health systems deliver more consistent, proactive healthcare every day. Cadence’s remote patient intervention solution couples powerful new technology with clinical excellence, providing its patients a precise and personal level of care all outside of the four walls of the hospital.At Cadence, we aim to exceed the expectations of our patients, clinicians, and partners every day. Our team values trust and autonomy, and we empower one another to make decisions, solve problems and build something better. We give clear, candid feedback with the utmost honesty and encouragement. If you’re interested in joining us, explore opportunities at www.cadence.care.
Job ID: 147759351
Skills:
Tcl, Python, Perl, routing, Synthesis, ASIC design flow, Timing Analysis, PPA optimization, EDA Tools, Placement, signoff, Timing Closure, RTL-to-GDSII
Skills:
routing, Perl, Python, Tcl, ASIC design flow, Synthesis, Timing Analysis, signoff, EDA Tools, Timing Closure, Placement, PPA optimization, RTL-to-GDSII
Skills:
Test Plan Creation, Automation Frameworks, Pcie, Nvme, Programming and scripting languages, System Design of SSD, Debugging and problem-solving skills, Verification and validation methodologies, Testbench architecture, NAND, Simulation and emulation environments
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