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Principal Product Engineer - Digital & Signoff Group (DSG)
Location: Bangalore
Team: Cadence DSG (Digital & Signoff Group)
The Opportunity
Join Cadence's Digital and Signoff Group (DSG) as a Product Engineer, where you will act as the vital bridge between R&D, Application Engineering, and our global customers. In this high-impact role, you will influence the next generation of chip design software, helping industry leaders solve complex physical design challenges at 7nm and below.
Key Responsibilities
Technical Expert: Serve as the primary place-and-route (P&R) resource for internal development teams and external customers. Product Evolution: Collaborate with R&D to track, diagnose, and resolve software issues, ensuring a robust tool release cycle. Design Benchmarking: Execute competitive benchmarks to demonstrate Cadence's edge in Power, Performance, and Area (PPA). Flow Innovation: Develop and deploy customized RTL-to-GDSII methodologies and scripts to meet specific customer design goals. Strategic Collaboration: Partner with Product Marketing to align technical capabilities with market needs and customer roadmaps.
Requirements
Education:
Bachelors in Electronics Engineering (EE) + 6 or more years of industry experience,
OR
Masters in Electronics Engineering (EE) + 4 or more year of digital implementation experience.
Core Expertise: Deep understanding of the full ASIC design flow (RTL-to-GDSII) with a focus on physical design and timing analysis. Advanced Node Experience: Proven hands-on experience with timing closure and PPA optimization at 7nm, 5nm, or below. Tool Proficiency: High familiarity with industry-standard EDA tools for synthesis, placement, routing, and signoff. Scripting Skills: Proficiency in Tcl, Python, or Perl (familiarity with AI-driven productivity tools is a major plus).
Communication: Strong verbal and written skills to translate complex technical issues into actionable solutions.
Job ID: 147675323
Skills:
Tcl, Python, Perl, routing, Synthesis, ASIC design flow, Timing Analysis, PPA optimization, EDA Tools, Placement, signoff, Timing Closure, RTL-to-GDSII
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