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www.EnchargeAi.com
Location : Bangalore (Hybrid-2 days-Office+3 days -Home ) or Remote (any where in India)
Title : Principal Physical Design Engineer
EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge's robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today's best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.
About the Role
We are seeking a highly experienced Principal Physical Design Engineer with a strong background in chip-level implementation and EDA tools. The ideal candidate will have deep expertise in physical design, timing closure, and low-power design.
Qualifications
Contact:
Uday
[Confidential Information]
www.mulyatech.com
Job ID: 144181899
Skills:
routing, Signal Integrity, CTS, floorplanning, Timing Closure, IR EM and variability analysis, Placement, low-power design, ASIC SOC physical design implementation, Physical Verification
Skills:
LVS, Advanced process technology nodes, Cadence layout tools, Ansys Redhawk-SC tool, Innovus, physical design implementation, Antenna with Caliber tool, Tempus, DRC, Physical verification closure, STA closure, PPA analysis, APR flow development, IR EM experience
Skills:
automation, Tcl, Python, Perl, RTL integration, advanced physical design methodologies, ASIC design flow, hierarchical physical design strategies, Synthesis, back-end physical design, modern EDA tools, Timing Closure, scripting using Makefile, Verification, AI ML-driven optimization
Skills:
static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis
Skills:
Tcl, Verilog, Python, Perl, Clock Tree Synthesis, object-oriented programming, Place And Route, EDA Tools, floorplanning, VHDL, RTL-to-GDSII implementation, Synthesis, Timing Closure
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