routing, Signal Integrity, CTS, floorplanning, Timing Closure, IR EM and variability analysis, Placement, low-power design, ASIC SOC physical design implementation, Physical Verification

LVS, Advanced process technology nodes, Cadence layout tools, Ansys Redhawk-SC tool, Innovus, physical design implementation, Antenna with Caliber tool, Tempus, DRC, Physical verification closure, STA closure, PPA analysis, APR flow development, IR EM experience

automation, Tcl, Python, Perl, RTL integration, advanced physical design methodologies, ASIC design flow, hierarchical physical design strategies, Synthesis, back-end physical design, modern EDA tools, Timing Closure, scripting using Makefile, Verification, AI ML-driven optimization

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

Tcl, Verilog, Python, Perl, Clock Tree Synthesis, object-oriented programming, Place And Route, EDA Tools, floorplanning, VHDL, RTL-to-GDSII implementation, Synthesis, Timing Closure