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Principal Engineer, Performance Modelling
Job Description
Key Responsibilities:
- Develop and maintain performance models for SoC designs using Synopsys Platform Architect or Emulation Platform.
- Collaborate with architecture, design, software, and verification teams to define performance requirements aligned with overall system goals.
- Analyze and optimize system performance, including DDR memory, CPU, GPU, interconnects, and high-speed interfaces such as PCIe and UCIe.
- Identify performance bottlenecks and propose solutions to improve system efficiency.
- Conduct performance simulations and provide detailed analysis and reports.
- Mentor and guide junior engineers in performance modeling and analysis techniques and best practices.
- Stay updated with the latest advancements in SoC performance modeling and industry solutions.
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Key Skills
About Company
Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier.As the industrys leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog Connectivity, and Power.
Skills:
Silicon Validation, system integration, SoC integration, controller configuration, Quality Of Service, DDR LPDDR controller IP, memory subsystem design, power management, Scheduling, memory architecture concepts, chiplet-based memory architectures, memory hierarchy optimization, LPDDR5X, Training, traffic modeling, Linux firmware bring-up, memory performance analysis, software-driven debug, system-level benchmarking, RAS features, DDR5, Validation, AI memory bandwidth optimization, LPDDR6, memory training algorithms
Skills:
Platform Architect, Soc Architecture, Cpu, Gpu, SoC performance modeling, Emulation Platform
Skills:
code coverage , memory controllers , C, Shell, Verilog, Flash, System Verilog, Python, Perl, Tcl, interconnect, CHI, Memory, UVM methodology, Microprocessor architecture, assertions, constrained random methodologies, SoC Verification, LPDDR5, Metric Driven Verification, Rom, formal verification methodologies, Axi, AHB, Ram