Silicon Validation, system integration, SoC integration, controller configuration, Quality Of Service, DDR LPDDR controller IP, memory subsystem design, power management, Scheduling, memory architecture concepts, chiplet-based memory architectures, memory hierarchy optimization, LPDDR5X, Training, traffic modeling, Linux firmware bring-up, memory performance analysis, software-driven debug, system-level benchmarking, RAS features, DDR5, Validation, AI memory bandwidth optimization, LPDDR6, memory training algorithms

Platform Architect, Soc Architecture, Cpu, Gpu, SoC performance modeling, Emulation Platform

code coverage , memory controllers , C, Shell, Verilog, Flash, System Verilog, Python, Perl, Tcl, interconnect, CHI, Memory, UVM methodology, Microprocessor architecture, assertions, constrained random methodologies, SoC Verification, LPDDR5, Metric Driven Verification, Rom, formal verification methodologies, Axi, AHB, Ram