conformal lec , Clp, Perl, Python, Tcl, Fusion Compiler, Formality, LEC, MCMM methodologies, UPF, Cadence Genus, Synthesis, Synopsys Design Compiler, RTL-to-GDS, CPF, Low Power Verification

ALM, JIRA, Selenium, Agile Scrum development process, Test Architecture, Iso 14971, IEC 62304, test automation frameworks, medical device software development, verification strategies

UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal

static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

needs assessment , Ms Office, Optioneering, Infoworks ICM, Urban drainage modelling, Model verification, Waste water modelling, Gis Software

scoreboard , Nvme, Pcie, Verilog, System Verilog, DDR, Assertions, Functional coverage coding, RTL debugging, Code Coverage analysis, Axi, AMBA protocols, Uvm, AHB

multidimensional designs, project management, Design Verification, layout of complex integrated circuits, component and system simulation, Vlsi Design, Problem Solving, architecture and logic design

Synthesis, multi-voltage design, floorplanning, SDC constraint development, MBIST, test specifications, Dfm, formal verification, Timing Closure, DRC, debug test coverage, Scan, ESD checks

ethernet ip , C, Fpga, Python, Rtos, Linux, ASIC, Communications Protocols, TCP-IP, Firmware Verification, Embedded Systems