needs assessment , Ms Office, Optioneering, Infoworks ICM, Urban drainage modelling, Model verification, Waste water modelling, Gis Software

synopsys tools , Verilog RTL coding, Power Compiler, formal verification tools, IC Compiler, primetime, Design Compiler, CMOS VLSI development, Digital Design

rtl verification , Perforce, Pytest, Sonarqube, Gitlab, Python, Git, Tcl, power management, Power Artist, UPF, Structural Low power design, Mixed signal power analysis, EDA Tools, Power Gating, Power-aware Simulation, Voltage regulators, Power Isolation, Power Island, Power analysis and optimisation methods, Prime-Power RTL, Low Power Methodology, Joules, Architectural analysis, ASIC design flows, Object-oriented programming in Python, VSCode

arm architecture , C, Usb, Tcl, Ethernet, Perl, Pcie, DDR, Uvm, Synopsys, scoreboards, BFM, TLMs in SystemC, eMMC, Mentor, monitors, Cadence, assertion-based formal verification tools, ARM verification tools, hardware emulation support

Unix, Shell, C, Linux, Perl, Verilog, Python, Uvm, systemverilog

Verification Methodologies, NVME architecture, PCIe transport and link layers, Post silicon debug, SoC Verification, C based SoC verification, Simulation, Testbench architecture, Pattern generation

Dft, Physical and formal Verification, exposure to frontend and Analog processes, backend flows for MCU or low-power SoC designs

static timing analysis, VHDL, clocking resets, Timing Analysis, verification methodologies, EDA tools for synthesis, digital IC ASIC design, RTL quality tools such as Spyglass Lint CDC RDC, RTL design using Verilog, low-power design techniques, Simulation