Principal Digital Verification Engineer

Required Skills

• Technical Proficiency:
• Expertise in #UVM methodology.
• Extensive experience in architecting and coding moderately complex UVM-based verification frameworks.
• Proficiency in #SystemVerilog coding.
• Demonstrated ability to code System Verilog Assertions (#SVA).
• Soft Skills:
• Must possess excellent problem-solving skills.
• Must have good communication skills and the ability to work effectively and collaboratively in a team environment.
• Must be self-motivated and committed to producing the best quality results.

Preferred Skills

• Scripting: Knowledge of and experience with scripting languages (e.g., Python, Perl, Tcl).
• Domain Knowledge: Experience working with memory products is highly preferable.
• Simulation Environment Expertise: Experience with mixed signal simulation environments is preferable.

Experience & Education

• Experience: Minimum of 10 years to 18Yrs experience in #UVM verification.
• Education: Bachelor's degree or higher in Electrical Engineering