Principal Design Engineer

Debugging, Test Planning, Simulation, systemverilog, Uvm, IP verification, Testbench development, Verification architecture, Mentoring

code coverage , closure , Ovm, Perl, Tcl Scripting, Verilog, SDF, automation, Specman, SV, assertions development, constraint randomization, RTL, Uvm, GLS, formal verification, eRM methodology, test-bench development, HVL

Scripting, Automotive FuSa, debug skills, GCM protocol, AI-assisted design tools, AES Encryption Decryption algorithm, PCIe design, Design Tools

Fcoe, Ethernet, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

System Design, Automotive