Job Description:
Cadence IP Group is seeking a professional grade Execution Engineer who can work with cross functional teams ranging from architecture, all aspects of Circuit design, Layout development, RTL design & Validation, Physical design & Test chip development.
Requirements:
- MS EE or higher
- 8-15 years of overall experience in ASIC Design & validation.
- Experience in working with or leading cross domain functions is a plus.
- Excellent communication and stakeholder management skills.
- Ability to make judgements on execution quality across all disciplines and make tradeoffs as needed between technical, schedule and other customer vectors of success.
- Prior hands on experience in DDR/LPDDR/GDDR or equivalent experience in Complex Mixed signal Phy (e.g. SerDes) development is required.
- Prior experience with post Silicon validation & customer IP deployment of one or more complex
Memory Interface IPs/Serial IO IPs is an added advantage.
