- The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
- Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
- The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success
- Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
- You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each otherevery day.
JOB Responsilibilities:
BE/BTECH/ME/MTECH
- The responsibility primarily entails leading pre and post Silicon Subsystem Prototyping, Validation and Hardware Design for Cadence High Speed SERDES Test chips.
- What we do :
- Pre Silicon emulation and Verification of System in NCSIM/Palladium/other Simulators.
- Hardware and Subsystem Board Design for all the Projects. (HW/SW infrastructure designed within team)
- Prototyping and Firmware Development for our High Speed Serdes like PCIe, CXL , UCIe, USB ,ethernet.
- Lead the Bring up, Debug, Compliance efforts and System level Characterization all the way to report release.
- Engage in interop and Customer Debug.
What you'll gain :
- Chance to work on cutting edge SERDES IP's from Cadence. Refer to Cadence Website for more details on our SERDES IP's.
- Tremendous learning curve on SERDES PHY, Controllers, Protocol and System integration.
- Hardware and Subsystem design expertise.
- Experience in deploying and debugging your Solutions in different customer environments.
What we are looking for :
Minimum Qualifications:
- 10-15 years (with Btech) or 10 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
- 2-3 years of management experience leading/mentoring a small team of engineers
- Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on PCIe/CXL/UCIe/Ethernet.
- Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
Preferred Qualifications:
- Experience leading System testing efforts for SERDES solutions.
- Experience in PCIe/UCIe LTSSM states is a plus.
- 1-2 years of experience in FPGA Design and Schematic design.
- 1-2 years of IP/SoC Physical Layer Electrical Validation experience is a plus.
- Familiarity with Verilog RTL coding for FPGA, python,C/C++
- Good communication skills
Seasoned Systems
- Validation engineer who can lead SERDES projects (PCIe/CXL/UCIe) and mentor Junior
