Post Silicon Validation Engineer

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MTS SILICON DESIGN ENGINEER

Role Overview

Responsible for verifying latest gen complex Ryzen CPU clusters/blocks using formal methods. You'll engage on creation of formal proofs, abstraction models, and verification strategies to ensure correctness, collaborating closely with architects, RTL designers, and validation teams.

Key Responsibilities

• Formal Verification & Proof Development
  • Perform formal verification (model checking, equivalence checking) on CPU microarchitecture/IP blocks.
  • Develop formal proofs, abstraction models, and convergence methodologies to maximize coverage and bug hunting.
• Test Planning & Strategy
  • Generate comprehensive formal verification plans: scope, coverage goals, strategy, and proof approaches.
  • Lead ROI analysis to balance formal vs. dynamic methodologies.
• Collaboration & Debugging
  • Work with architects, RTL designers, and verification teams to resolve failing assertions and improve design quality. Look for potential sign-off for critical blocks to guarantee exhaustive proof and reduce silicon escapes.
  • Support post-silicon failure debug and sighting resolution when required.
• Methodology & Infrastructure Development
  • Maintain and enhance formal infrastructure (flows, abstraction techniques, tools)
  • Investigate new formal techniques and define reusable verification methodologies for the team

Qualifications & Skills

Education

• Bachelor's, Master's, or Ph.D. in Computer Engineering, Electrical/Electronic Engineering, Computer Science, or related field.

Experience

• 5-10 years exp in formal verification for logic/microarchitecture IP- preferably CPU-related.
• Proven experience using formal engines (e.g. JasperGold, VC Formal) for bug hunting.
• Skilled in assertion languages (SystemVerilog Assertions) and HDL modeling (Verilog/VHDL/SV)
• Strong scripting or programming ability (Python, Tcl, Perl)

Soft Skills

• Analytical mindset with intellectual curiosity ability to uncover hidden verification gaps.
• Exceptional communicator and collaborator in cross-functional environments.
• Mentorship or technical ownership experience-leading reviews and guiding junior engineers.

Preferred

• Deep understanding of CPU microarchitecture topics (in-order/out-of-order execution, pipelines, memory consistency, coherence, ISA, security, floating-point, etc.)
• Advanced degree (M.S. or Ph.D.) specializing in formal methods or microarchitecture.
• Experience with CPU post-silicon validation and debug.
• Familiarity with SoC verification flows, security IPs (e.g., secure enclaves), or system-level proof approaches.

Why This Matters

This role is pivotal in ensuring the correctness and robustness of CPU designs by leveraging rigorous formal verification methods. As CPU microarchitectures grow more complex-with deeper pipelines, wider issue widths, and intricate memory hierarchies-formal techniques are essential to catch subtle bugs early and guarantee product reliability.

#LI-BM2

Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available

This posting is for an existing vacancy.