Physical Verification Engineer

Job Role : PV CAD Engineer

Experience : 6 to 12 years

Location : Hyderabad

Role Summary

We are looking for an experienced Physical Verification (PV) and IR/EM Engineer with hands‑on experience in advanced‑node SoC designs. The role involves full‑chip and block‑level ownership of PV signoff and power integrity (IR/EM) analysis, working closely with PD, CAD, and foundry teams to ensure first‑time‑right silicon. Knowledge on 3DIC Phy/IR-EM especially is a fetch for the role.

Responsibilities

Physical Verification (PV)

· Own block‑level and full‑chip PV signoff including DRC, LVS, ERC, and DFM checks.

· Debug and resolve complex DRC/LVS violations in large SoC designs.

· Drive PV convergence strategies for advanced nodes (N3/N5/N6).

· Work with PD and CAD teams to define robust PV flows and methodologies.

· Review and interpret foundry rule decks (PDK updates) and drive necessary flow changes.

· Support tape‑out readiness and milestone exits (NLB / NLC / NLD).

IR / EM / Power Integrity

· Own static and dynamic IR drop analysis at block and full‑chip levels.

· Perform Signal EM and Power EM analysis, including RMS and peak checks.

· Identify systematic power integrity issues and drive architectural/layout fixes.

· Collaborate with clock, RDL, packaging, and 3DIC teams for power grid robustness.

· Review and apply waivers / guidelines in coordination with CAD, DFP, and foundry teams.

· Support aging, reliability, and FIT analysis as required.

Cross‑Functional & Leadership

· Act as technical interface between PD, CAD, DFP, and foundry.

· Provide technical guidance and mentoring to junior engineers.

· Drive best practices, automation, and flow improvements.

· Contribute to post‑silicon learning feedback for future designs.

Requirements

· Experience with Full-chip signoff on high-performance SOCs & TSMC foundries preferred.

Strong hands‑on experience in: DRC, LVS, ERC, DFM signoff, Static & Dynamic IR drop analysis, Signal EM / Power EM analysis

· Expertise with industry tools: Cadence: Innovus, Voltus, Pegasus & Synopsys: ICC2, ICV, PrimeRail (or equivalent)

· Solid understanding of: Advanced node design rules (N3/N5/N6), Power grid design and clock distribution & Foundry PDKs and signoff requirements

· Scripting skills in TCL / Python / Perl for flow automation.

· Strong debugging, data analysis, and problem‑solving skills.