Company Description
Cognitive Design Technology, established in 2007, is a leading technology solution provider in India serving the high-tech industry. The company offers a wide range of products, training, design services, and consultancy in advanced technology domains such as semiconductor, embedded systems, CAD, MEMS, and nanotechnology. With its cutting-edge solutions in VLSI, SoC design, ASIC, FPGA, IC packaging, CMOS process simulations, and more, the company addresses the latest industry requirements. Cognitive Design Technology works in partnership with global technology leaders, ensuring customer satisfaction through comprehensive and competitive solutions.
Role Description
We are seeking a motivated and technically strongPhysical Design Engineerwith 3+ years of experience inPD implementation and Static Timing Analysis (STA). The candidate will be responsible for executing end-to-end physical design flows for advanced technology nodes, ensuring timing closure, power optimization, and high-quality layout delivery for complex SoCs and IP blocks.
Location: Chennai, Tamilnadu
Employment Type : Full-Time
Experience Level : 3+ Years
Key Responsibilities
- Perform full-chip and block-level physical design implementation from netlist to GDSII.
- Execute floorplanning, power planning, placement, CTS, routing, and optimization.
- Perform static timing analysis and timing closure at block and top level.
- Debug and resolve setup, hold, max transition, max capacitance, and noise violations.
- Work on congestion, IR drop, and EM analysis and fixes.
- Support physical verification including DRC, LVS, and antenna checks.
- Collaborate with synthesis, DFT, and RTL teams to resolve design issues.
- Develop and maintain PD flow scripts and automation.
- Participate in design reviews and provide technical feedback.
Required Qualifications
- Bachelor's/Master's degree in Electronics / Electrical / VLSI Engineering or related field.
- Minimum 3 years of hands-on experience in physical design and STA.
- Strong understanding of digital design fundamentals and CMOS technology.
- Experience working on advanced nodes (e.g., 28nm and below preferred).
Required Technical Skills
Physical Design
- Floorplanning, Placement, CTS, Routing, Optimization
- Multi-mode Multi-corner (MMMC) design methodology
- Low-power implementation (UPF/CPF awareness)
Static Timing Analysis
- Setup/hold analysis
- On-chip variation (OCV, AOCV, POCV)
- Clock domain crossing (CDC) concepts
- Timing ECO generation and implementation
Tools
- Industry-standard PD and STA tools (e.g., Innovus / ICC2, PrimeTime or equivalent)
- Physical verification tools for DRC/LVS
- Scripting: Tcl, basic Python or Shell
Preferred Qualifications
- Experience with full-chip timing closure.
- Knowledge of power integrity (IR/EM) analysis.
- Familiarity with DFT-aware implementation.
- Exposure to sign-off flows.
Soft Skills
- Strong analytical and debugging ability
- Good communication and documentation skills
- Ability to work independently and in teams
- High ownership and delivery-focused mindset
What We Offer
- Competitive compensation and benefits
- Exposure to cutting-edge semiconductor technologies
- Career growth and technical learning opportunities
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