Clock Tree Synthesis (CTS), Routing, IR/EM analysis, floorplanning, Hierarchical and flat implementation flows, Physical Verification, Cadence Innovus, Timing analysis and optimization, Signoff methodologies, Timing Closure, Low-power implementation techniques, Signal Integrity, Noise issues

congestion management , Python, Routing, Perl, Tcl, Sta, CTS, Advanced Floorplanning, Cadence Innovus, Physical Signoff, LVS, Fusion Compiler FC, UPF, MMMC, Power Distribution Network, Antenna, Multi-voltage design implementation, Placement Optimization, EM, Physical Verification, Ir, low power design, Physical Design, Timing Closure, ECO Implementation, DRC

power integrity , Routing, CTS, primetime, Fusion Compiler, floorplanning, ICC2, PDN Placement, Physical Verification, Calibre, Innovus, SoC ASIC Physical Design, Timing Closure, signoff methodologies

Synopsys - ICC, Shell scripting, Tcl, Routing, Perl, Power grid analysis, Timing Closure, Place and Route tools, Antenna fixing, Floorplan, DRC-LVS closure, Signal Integrity, Placement, Physical Design, Cadence – Innovus Encounter