Perl, Python, Tcl, low-power physical design implementation, STA electrical checks, top-level floorplanning, ASIC Design, Physical Verification, block integration

Python, Routing, Perl, Tcl, physical design methodologies, CTS, floor-planning, Synopsys Fusion Compiler, PPA tradeoffs, LVS, Calibre, Physical Verification, Extraction, StarRC, floor plan synthesis, Synthesis, Apache Redhawk, CPU physical design, EM, Ir, signoff, Place And Route, DRC, Timing Closure, Placement, Cadence PrimeTime

power integrity , Unix, routing, Linux, Python, Tcl, CTS, Extraction, floorplanning, power grid architectures, signoff, Cadence Voltus, static and dynamic IR-drop analysis, Ansys RedHawk, physical signoff flows, Placement, electromigration signoff, EM IR analysis, decoupling strategies

Perl Scripting, Tcl, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, High Frequency Design, Power Gating, PDN Methodology, PPA Targets, Timing Signoff

Python Scripting, Shell, Perl, Verilog, Tcl, Physical Design, Signoff, VHDL, IP integration, Full-chip aspects, Timing Verification

Python, Tcl, primetime, Dft, PT-DMSA, timing congestion, ECO generation flow, IO Timing interface budgeting, ASIC timing constraints generation