We are looking for an experienced Physical Design Engineer / Lead with strong hands-on expertise in block-level physical design, timing closure, and signoff using Cadence Innovus and related EDA tools.
The ideal candidate will own the complete Netlist/RTL to GDSII flow, drive signoff closure, and provide technical leadership to a small team while acting as a key point of contact for clients.
Key Responsibilities
Own block-level Physical Design implementation from RTL/Netlist to GDSII
Handle complete PnR flow, including floorplanning, placement, CTS, routing, and optimization
Perform block-level timing signoff, ECO generation, and closure
Drive block-level physical and power signoff
Execute and sign off STA, DRC, LVS, IR/EM, and other physical verification checks
Collaborate with cross-functional teams to resolve issues related to:
Constraints validation
STA
Physical verification
Design and methodology challenges
Contribute to PD methodology development and flow improvements
Ensure projects meet functional, technical, and schedule requirements
Act as client-facing technical point of contact
Provide technical guidance and mentorship to junior engineers
Lead and manage a small project team of 46 engineers
Required Skills & Experience
Strong experience in Physical Design (Netlist/RTL to GDSII)
Hands-on expertise with Cadence Innovus / Encounter
Strong knowledge of Synthesis, STA, Timing Closure, ECOs
Experience with signoff tools:
i. Tempus, PTSI
ii. Calibre, PVS
iii. Talus
iv. Conformal
Solid understanding of physical verification and signoff methodologies
Proficiency in automation and scripting:
Tcl, Perl, Python, Awk
Proven experience leading small teams or modules
Strong communication skills with ability to interact directly with clients
Nice To Have
Experience in advanced technology nodes
Exposure to low-power designs and power optimization techniques
Prior experience in customer-facing or onsite-offshore models
