Physical Design Engineer, Staff

• Plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.
• Collaborate with cross-functional teams to develop solutions and meet performance requirements.
• Hands-on Physical Design (PD) execution at block/SoC level with a focus on Power, Performance, Area (PPA) improvements.
• Strong understanding of technology and PD Flow Methodology enablement.
• Work with Physical Design engineers to roll out robust methodologies, identify areas for flow improvement (area/power/performance/convergence), develop plans, and deploy/support them.
• Provide tool support and issue debugging services to physical design team engineers across various sites.
• Develop and maintain 3rd party tool integration and productivity enhancement routines.
• Understand advanced technology Place & Route (PNR) and Static Timing Analysis (STA) concepts and methodologies, and work closely with EDA vendors to deploy solutions.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
• OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
• OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Skill Set:

• Strong programming experience & Proficiency in Python/Tcl/C++.
• Understanding of physical design flows using Innovus/fc/icc2 tools.
• Knowledge of one of Encounter/Innovus or FC (or other equivalent PNR tool) is mandatory.
• Basic understanding of Timing/Formal verification/Physical verification/extraction are desired.
• Ability to ramp-up in new areas, be a good team player, and excellent communication skills desired.

Experience:

• 3-5 years of experience with the Place-and-route and timing closure and power analysis environment is required.