Physical Design Engineer
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1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation
2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology)
3. Implementation of a project with the full Cadence tools
4. Have worked on complex Hard macros with SerDes and/or critical in timing and area
5. Having experience in Flip-Chip SoC bump Ios)
6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file
SmartSoC Solutions is emerging as a leader in providing engineering solutions worldwide. We offer end-to-end Semiconductor, Embedded, Automotive and System Design to design and build next-generation leadership products under one roof. And allowing clients to achieve both quick wins and long-term results.
Our goal is to be an extended arm of engineering product and IT companies and ensure good quality productization cost-effectively.
Job ID: 113016793
Skills:
Python, RHSC tool, EMIR signoff, IR Power-Domain-Network signoff, Physical Implementation Synthesis, Place Route
Skills:
Routing, Python, Tcl, CTS, floorplanning, Placement Optimization, Antenna Density, LVS, Power Planning, IC Validator, Calibre, Physical Verification, Signoff Closure, Physical Design, ERC, Timing Closure, ECO Implementation, DRC
Skills:
cadence encounter , Unix Linux, SDC STA and Equivalence checking, Flow automation, Synopsys ICC2 tool set, Block SoC level Physical Design, PnR tools like ICC2 Innovus, SKILL Shell, 14nm 10nm 7nm 5nm process nodes, Tapeout sign-off experience, Python Script
Skills:
Physical Design, DFT Implementation, Layout Extraction, Rtl Design
Skills:
rc extraction , routing, DRC, block level low power aware floorplanning, tape out activities, LVS, Cadence layout tools, Placement, Innovus, IR EM analysis, Tempus, ERC, STA timing closure, Caliber tool, Clock Tree Synthesis
