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1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation
2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology)
3. Implementation of a project with the full Cadence tools
4. Have worked on complex Hard macros with SerDes and/or critical in timing and area
5. Having experience in Flip-Chip SoC bump Ios)
6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file
SmartSoC Solutions is emerging as a leader in providing engineering solutions worldwide. We offer end-to-end Semiconductor, Embedded, Automotive and System Design to design and build next-generation leadership products under one roof. And allowing clients to achieve both quick wins and long-term results.
Our goal is to be an extended arm of engineering product and IT companies and ensure good quality productization cost-effectively.
Job ID: 113016793
Skills:
IR drop, digital design fundamentals, LVS, Cadence Innovus, Physical Verification, crosstalk, MMMC setup and hold closure, block-level timing analysis, physical design implementation, AI-assisted tools, DRC, EM noise, Synopsys IC Compiler II
Skills:
Innovus, PnR Engineer
Skills:
Place Route, RHSC tool, IR Power-Domain-Network signoff, EMIR signoff, Physical Implementation Synthesis, scripting – python
Skills:
cadence encounter , Unix Linux, 14nm 10nm 7nm 5nm process nodes, Synopsys ICC2 tool set, Flow automation, PnR tools like ICC2 Innovus, SDC STA and Equivalence checking, SKILL Shell Python Script, Tapeout sign-off experience
Skills:
Perl, Ruby, Blocklevel, Toplevel Physical implementation, Lower node technologies, EDA Tools
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