Block level and Top-level physical implementation, Place and Route processes, Physical Design, Synthesis for high-speed designs

Python, RHSC tool, EMIR signoff, IR Power-Domain-Network signoff, Physical Implementation Synthesis, Place Route

Routing, Python, Tcl, CTS, floorplanning, Placement Optimization, Antenna Density, LVS, Power Planning, IC Validator, Calibre, Physical Verification, Signoff Closure, Physical Design, ERC, Timing Closure, ECO Implementation, DRC

cadence encounter , Unix Linux, SDC STA and Equivalence checking, Flow automation, Synopsys ICC2 tool set, Block SoC level Physical Design, PnR tools like ICC2 Innovus, SKILL Shell, 14nm 10nm 7nm 5nm process nodes, Tapeout sign-off experience, Python Script

Physical Design, DFT Implementation, Layout Extraction, Rtl Design

rc extraction , routing, DRC, block level low power aware floorplanning, tape out activities, LVS, Cadence layout tools, Placement, Innovus, IR EM analysis, Tempus, ERC, STA timing closure, Caliber tool, Clock Tree Synthesis