Block level and Top-level physical implementation, Place and Route processes, Synthesis for high-speed designs, Physical Verification, Physical Design for complex Chiplets, Unix/Linux environment

Routing, power analysis, Synthesis, EMIR, floorplanning, Placement, Physical Design Implementation, Power Planning

cadence encounter , Unix Linux, 14nm 10nm 7nm 5nm process nodes, SDC STA and Equivalence checking, Synopsys ICC2 tool set, PnR tools like ICC2 Innovus, Flow automation exposure, SKILL Shell, Tapeout sign-off experience, Python Script

Routing, Python, Tcl, CTS, floorplanning, Placement Optimization, Antenna Density, LVS, Power Planning, IC Validator, Calibre, Physical Verification, Signoff Closure, Physical Design, ERC, Timing Closure, ECO Implementation, DRC

Block level and Top-level physical implementation, Place and Route processes, Physical Design, Synthesis for high-speed designs

Place Route, RHSC tool, EMIR signoff, scripting – python, Physical Implementation Synthesis, IR Power-Domain-Network signoff