clock distribution , Clp, PERL, Tcl, low power design, Sta, PERC, Signal Integrity Analysis, LVS, LEC flow, Tape Out, IP integration, Dfm, Timing Closure, Physical Verification, Synthesis, Gds, Tk, cpf, Clock Tree Synthesis, upf, PNR, Physical Design, ERC, DRC, Floorplan

Perl, Verilog, Python, Tcl, power analysis optimization, power gating, Simulation, clock gating, systemverilog, UPF CPF methodologies, DVFS implementation, low-power checking tools, formal verification, RTL gate-level and physical design, EDA Tools, low-power design techniques, low-power verification flows, power performance and area PPA targets, multi-voltage

PnR-Floorplan Macro placement, EM IR understanding and fixes, STA analysis, Util area reduction experiments, ECO cycle, Density Congestion Timing issues and fixes on lower tech nodes 5nm, Physical aware Synthesis using FC, PV closure

Unix, Linux, Perl, Tcl, Low power verification, floorplanning, Placement, power analysis, PNR implementation

routing, floor-planning, physical design flows, digital VLSI concepts, Tempus, Timing Analysis, Cadence Innovus, Voltus, Logic Synthesis, Rtl Design, EDA Tools, Timing Closure, Placement, Cadence simulation tools

physical verification using ICV, Innovus, VLSI Physical Design flows, Fusion Compiler, Synopsys Cadence Physical Design tools

power optimization , Perl, Scripting, Python, Tcl, Cadence, Mentor, Timing Analysis, Physical Design, Signal Integrity, EDA Tools, Synopsys

redhawk , primetime, PDN methodology, floorplanning, physical design implementation, STA constraints, Tempus, Cadence Innovus, IR EM mitigation, Physical Verification, Voltus, signoff tools, Synopsys ICC2