rc extraction , Ecos, Perl, Tcl, Sta, Scan Insertion, Physical Verification, LVS, Cadence synthesis, RTL-GDSII, Timing analysis and verification, Synthesis, PNR, Physical Design, DRC, Antenna, Cross talk, formal verification, IR-EM checks, Place And Route, Timing Analysis

synopsys primetime , Scripting, Shell, Perl, Python, Tcl, Siemens Calibre, IR drop, Fusion Compiler, Cadence Tools, Power Reliability, ICC2, Tempus, LVS, Innovus, Physical Verification, Timing Analysis, ERC, Physical Design Tools, Synopsys Design Compiler, Genus, DRC, EM noise analysis

routing, floor-planning, physical design flows, digital VLSI concepts, Tempus, Timing Analysis, Cadence Innovus, Voltus, Logic Synthesis, Rtl Design, EDA Tools, Timing Closure, Placement, Cadence simulation tools

physical design methodologies, ASIC design flows, power gating, sign-off optimizations, Floorplan, deep sub-micron technology, multi-voltage domains, Circuit Design, device physics, Netlist2GDS

Voltus, Backend Signoff flows, Cell EM, LVS, SigEM, Power Grid planning, pegasus, Cadence Tools, Innovus, PERC, EMIR, Tempus, Esd, Signal and Power bump planning, DRC

rc extraction , Ecos, Sta, Scan Insertion, Physical Verification, LVS, Cadence synthesis, RTL-GDSII, Timing Closure, Dft, Synthesis, PNR, DRC, Physical design flow, Cross talk, Verification Tools, formal verification, IR-EM checks, Place And Route, Timing Analysis

Routing, Static Timing Analysis, Low Power Synthesis, Signoff, Low Power Designs, Logical Physical Aware Synthesis, High-performance digital designs, Power Signoff, Advanced low power design techniques, UPF, Custom ASIC flows, Synthesis, Physical Verification, formal verification, Placement, Clock Tree Synthesis, CPF, Floorplan, Physical Design

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, Cadence Virtuoso, 3DIC implementation methodologies, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

static timing analysis, Physical Design, Floor Planning, ASIC designs, Sta