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Hi All,
Tech Mahindra hiring Physical Design Engineers for Bangalore
Exp: 7-10yrs
Location: Bengaluru
NP: 0-60days
JD:
We are looking for a profile with around 7 yrs of experience for PD, who has good exposure to PnR/ECO/signoff methodologies and capable of handling a medium complexity block independently!
If interested, please share your updated CV to [Confidential Information]
Job ID: 145174489
Skills:
cadence encounter , Unix, Shell, Linux, Flow automation, Synopsys ICC2 tool set, Physical Design, SDC STA, Python Script, PnR tools like ICC2 Innovus, Equivalence checking, Skill
Skills:
power optimization , C, Linux, Perl, Unix Shell, Tcl, Advanced STA Concepts, Physical Design Flow, Block level PnR convergence, Timing Convergence, Cadence Innovus, LVS, PTSI Tempus, Physical Verification, formal verification, Timing Closure, DRC, PDN, Floor-planning, Place And Route, Synopsys ICC2
Skills:
Scripting, Static Timing Analysis, Routing, Design Compiler, primetime, ICC2, Synopsys Fusion Compiler, LVS, Cadence Genus, Innovus, Physical Verification, Extraction, Formal Equivalence, StarRC, Placement, Floor-plan Physical Implementation, RTL to GDS2 flow, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Physical Design, Timing Closure, DRC, PNR tools
Skills:
clock distribution , Tcl, Clp, PERL, Gds, Synthesis, IP integration, Power and Signal Integrity Analysis, Physical Design, Clock Tree Synthesis, ERC, DRC, PNR, Tape Out, Extraction, upf, Dfm, Timing Closure, low power design, LVS, Physical Verification, cpf, Floorplan, Sta, PERC, Tk, LEC flow
Skills:
Static Timing analysis, Perl, Tcl, Clock Planning, SoC designs, Power Plan, Digital place and route, Floor Planning, Clock Tree Synthesis, Parasitic Extraction, PnR Signoff
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