cadence encounter , Unix, Shell, Linux, Flow automation, Synopsys ICC2 tool set, Physical Design, SDC STA, Python Script, PnR tools like ICC2 Innovus, Equivalence checking, Skill

power optimization , C, Linux, Perl, Unix Shell, Tcl, Advanced STA Concepts, Physical Design Flow, Block level PnR convergence, Timing Convergence, Cadence Innovus, LVS, PTSI Tempus, Physical Verification, formal verification, Timing Closure, DRC, PDN, Floor-planning, Place And Route, Synopsys ICC2

Scripting, Static Timing Analysis, Routing, Design Compiler, primetime, ICC2, Synopsys Fusion Compiler, LVS, Cadence Genus, Innovus, Physical Verification, Extraction, Formal Equivalence, StarRC, Placement, Floor-plan Physical Implementation, RTL to GDS2 flow, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Physical Design, Timing Closure, DRC, PNR tools

clock distribution , Tcl, Clp, PERL, Gds, Synthesis, IP integration, Power and Signal Integrity Analysis, Physical Design, Clock Tree Synthesis, ERC, DRC, PNR, Tape Out, Extraction, upf, Dfm, Timing Closure, low power design, LVS, Physical Verification, cpf, Floorplan, Sta, PERC, Tk, LEC flow

Static Timing analysis, Perl, Tcl, Clock Planning, SoC designs, Power Plan, Digital place and route, Floor Planning, Clock Tree Synthesis, Parasitic Extraction, PnR Signoff

Dc, Electrical checks, PnR tools, STA tools, Physical Verification, ICC, Chip tape outs, Physical Design, Innovus, Sign-off optimizations, Genus, Sign-off convergence