clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff

redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus

redhawk , Tcl, Perl, Python, Scripting Languages, PrimeTime PT, Physical Verification, floorplanning, Physical Design, Tempus, STA closure, Genus, HM-level PV, ECOs for timing convergence, PDN design, low-power design methodologies, Tweaker, STA signoff checks, Innovus, Clock Tree Synthesis CTS, voltage islands, LEC low-power checks, Place Route PNR, Voltus, Fusion Compiler FC, IR drop analysis

cadence encounter , Shell, Unix, Linux, Flow automation, Python Script, SDC STA and Equivalence checking, Tapeout sign-off experience, 10nm 7nm 5nm process nodes, Synopsys ICC2 tool set, Physical Design, PnR tools like ICC2 Innovus, Skill

routing, Sta, CTS, ECO execution, Pv, floorplanning, Dfm, constraints synthesis, Dft, Si, Timing Closure, block-level PnR, Netlist to GDS flow

EM IR understanding and fixes, PV closure, Util area reduction experiments, Physical aware Synthesis using FC, ECO cycle, STA analysis, PnR-Floorplan Macro placement, Density Congestion Timing issues and fixes on lower tech nodes 5nm