Unix, Linux, Perl, Tcl, Low power verification, floorplanning, Placement, power analysis, PNR implementation

Physical Design Planning, Placement, Floor Planning

Routing, Perl, Python, Tcl, CTS Clock Optimization, floorplanning, Placement Optimization, IR EM, Synopsys Fusion Compiler, Cadence Innovus, Physical Signoff, Power Planning, Eco, MMMC, PPA Optimization, STA Timing Closure, VLSI Physical Design, Synopsys ICC2

Python, Tcl, Synopsys Fusion Compiler, primetime, StarRC, ICC2, DSO.ai

Clp, Sta, Timing Constraints, RTL synthesis, LEC, low-power design concepts