Physical Design Engineer

Job Summary

We are seeking a skilled Physical Design Engineer with approximately 4 years of hands-on experience in the full-chip or block-level physical implementation of ASIC/SoC designs. The ideal candidate will have strong expertise in physical design flows, timing closure, and signoff activities for advanced technology nodes.

Key Responsibilities

• Perform block-level and/or full-chip physical design implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
• Own timing closure across all implementation stages (pre-CTS, post-CTS, post-route)
• Handle congestion, IR drop, and power optimization
• Run and debug DRC, LVS, and physical verification issues
• Perform ECO implementation to address timing, power, and functional fixes
• Work closely with RTL, STA, DFT, and Signoff teams to resolve design issues
• Analyze and fix timing violations (setup, hold, DRV) across multiple modes and corners
• Support signoff checks such as STA, SI, IR/EM, and power analysis
• Contribute to flow improvements, methodology documentation, and automation scripts

Required Skills & Qualifications

• 4+ years of experience in ASIC/SoC Physical Design
• Strong understanding of PD flow:
• Floorplanning
• Placement & optimization
• CTS
• Routing
• Timing closure
• Hands-on experience with EDA tools, such as:
• Synopsys: ICC2, PrimeTime, StarRC
• Cadence: Innovus, Tempus (or equivalent)
• Solid understanding of:
• STA concepts (setup, hold, OCV, AOCV, POCV)
• Low-power design techniques (clock gating, multi-Vt cells)
• Physical effects (IR drop, EM, crosstalk)
• Experience working on advanced nodes (28nm and below preferred)
• Good scripting skills in Tcl, Perl, or Python

Preferred Qualifications

• Experience with full-chip integration and top-level closure
• Exposure to low-power signoff flows (UPF/CPF)
• Familiarity with DFT and scan-related physical constraints
• Experience in high-frequency or low-power designs
• Good communication skills and ability to work in cross-functional teams

Education

• Bachelor's or Master's degree in Electronics / Electrical Engineering or related field