Tcl Scripting, place route flows, LVS, sign-off methodologies, floorplanning, wire planning, DFT methods, Synthesis, physical design verification, Timing Closure, DRC, custom clock trees, Clock Tree Synthesis, Tessent flow

Tcl, Perl, Routing, Python, OCV, Placement optimization, Physical effects, EDA Tools, EM, setup hold, crosstalk, IR drop, floorplanning, primetime, Tempus, Synopsys ICC2, scripting skills, AOCV, Timing Closure, Cadence Innovus, clock gating, multi-Vt cells, CTS, ASIC SoC Physical Design, PD flow, STA concepts, POCV, StarRC, Low-power design techniques