Unix, Linux, Perl, Tcl, Low power verification, floorplanning, Placement, power analysis, PNR implementation

C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation

Physical Design Planning, Placement, Floor Planning

layout verification , very large scale integration (VLSI) design, system on a chip (SoC), System Verilog, clock voltage domain crossing design for testing DFT, ASIC Design, design rules, low power designs

Python, Tcl, Synopsys Fusion Compiler, primetime, StarRC, ICC2, DSO.ai

routing, Sta, CTS, ASIC PD methodologies, digital design fundamentals, Extraction, Floor Planning, PNR, Placement, EM IR closure, signoff