Physical Design Architect

Physical Design Architect

Location: Bengaluru, India

Experience: 10–15 Years

Role Summary

We are looking for a seasoned Physical Design Architect to lead implementation and signoff strategies for complex SoCs, CPUs, and high-performance IPs on advanced technology nodes. The role requires deep expertise in physical design convergence, PPA optimization, and tapeout execution.

Key Responsibilities

• Define physical design architecture, floorplanning, partitioning, and implementation strategies.
• Drive full-chip/subsystem physical design from floorplan through signoff.
• Lead timing closure, CTS, congestion management, power planning, and ECO execution.
• Collaborate with Architecture, RTL, DFT, and Packaging teams to achieve PPA targets.
• Own signoff closure including STA, IR/EM, SI, DRC, LVS, and reliability analysis.
• Develop scalable methodologies and automation to improve design productivity.

Required Qualifications

• 10–15 years of Physical Design experience with multiple successful tapeouts.
• Strong expertise in Floorplanning, P&R, CTS, STA, MCMM optimization, and Physical Verification.
• Hands-on experience with Synopsys ICC2/Fusion Compiler, PrimeTime, Cadence Innovus/Tempus, and Calibre.
• Strong understanding of advanced nodes (7nm/5nm/3nm and below).
• Proficiency in Tcl, Python, or Perl scripting.

Preferred

• Experience with CPU, GPU, AI/ML, or high-performance SoC designs.
• Expertise in low-power design, power integrity, and advanced packaging technologies.

Join us to architect next-generation silicon and drive world-class physical design execution from concept to tapeout.