power optimization , hierarchical design, Physical Verification, electromigration, sign-off, floorplanning, full-chip physical design methodologies, Synthesis, Timing Closure, design closure strategies, partitioning, power analysis, SoC physical design

Perl, Python, Tcl, primetime, RTL-to-GDS recipes, Physical Design, Fusion Compiler, Synopsys Fusion Design Platform, IC Compiler II, AI ML optimization tools, Synopsys DSO.ai

caliber , Clp, Tcl, Python, Synopsys Fusion Compiler, UPF, Signoff, multi-voltage, PD tools and flows, Cadence Innovus, low power flows, Sta, ICC2, primetime, physical design implementation, ICV, Tempus, Synthesis, multi-Vt, PNR, Ansys RedHawk, RTL-to-GDSII flows