KEY RESPONSIBILITIES:
- Design synthesis: Performing logical and physical synthesis of blocks in IP
- Design analysis: Analyzing and verifying that the design meets requirements for functionality, performance, and area
- Design constraints: Defining synthesis design constraints and resolving STA issues
- Timing analysis: Analyzing timing arc and liberty quality, and providing suggestions for fixing timing violations
- Design quality checks: Completing all design quality checks and data quality checks (CDC/RDC/LINT/No clock flops etc)
- Collaboration: Working with RTL engineers to fix timing issues
- Tool evaluation: Driving new tool evaluation and methodology refinement
- ECO Implementation :Develop/enhance auto ECO generation scripts for timing closure and ECO implementation
- Power: Low power optimizations/UPF
PREFERRED EXPERIENCE:
Synthesis engineers should have prior experience with:
- Synopsys tools for ASIC synthesis and timing constraints
- Strong background in Timing analysis and CDC
- Experience in CDC/RDC/LINT closure
- Familiar with power intent definition, implementation (UPF)
- Knowledge of various implementation and architectural techniques for low power optimization.
- Verilog and System Verilog
- Perl/TCL/Makefile scripting
- Power Analysis using Power Artist and PTPX
- LEC, LP signoff tools
- VLSI front end design steps
- Good communication skills and ability to work with global teams
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering and 7+ years of work experience
