MNC Hiring: MTS Silicon Design Engineer DFT
Immediate Joiners Preferred !
Location: Hyderabad (Xilinx) / Remote (Flexible)
Experience: 612 Years
We are looking for an experienced MTS Silicon Design Engineer with strong expertise in DFT Architecture and VLSI Testing to join our team. If you are passionate about scan compression, MBIST, SoC-level DFT implementation, and production test readiness - this role is for you!
Key Technical Skills Required
- Strong fundamentals in Digital Logic Design and DFT Architecture
- Proficiency in HDL (Verilog / VHDL) for RTL design and analysis
- Solid understanding of VLSI testing principles, fault models & DFT methodologies
- Hands-on experience in:
- Scan Compression at IP level
- Scan Retargeting at SoC level
- SSN knowledge (Good to have)
- Experience with industry-standard tools:
- Tessent TestKompress
- Tessent Diagnosis
- MBIST tools
- RTL & gate-level simulation environments
- Working knowledge of FPGA architectures and synthesis flows
- Linux-based development environment experience
- Scripting skills (Perl / TCL / Python) Strong plus
Key Responsibilities
- Partner with RTL teams to define and ensure correct DFT architecture insertion
- Develop & verify robust DFT schemes for hard IPs and FPGA designs
- Own scan compression & ATPG for multiple fault models (stuck-at, transition, path-delay)
- Develop and validate MBIST architectures
- Debug scan/MBIST issues on bench and ATE
- Collaborate with NPI, Test Engineering & Product teams
- Support yield improvement and diagnosis
- Optimize test methodologies for cost & coverage
- Mentor team members and drive best practices
Qualifications
- Bachelor's / Master's in Electrical / Electronics / Computer Engineering
- Formal training in Digital Design / DFT preferred
- Tessent Scan / ATPG / MBIST certifications are a plus
