You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBLITIES:
- Strong knowledge in IP/SOC design methodologies.
- Power aware verification expertise using UPF (Unified Power Format)
- Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog
- Mentoring juniors and enhancing their skill set
- Must have strong knowledge of AMBA AHB/AXI protocol
- Working knowledge on code coverage, functional coverage, Lint, CDC etc
- IP development and coding using standard coding guide lines knowledge
- Excellent communication skills. Must be able to particpate lead in global meetings
- Soft skills to be able to work in a cross functional international team digital and software design engineers
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requireme
PREFERRED EXPERIENCE:
- 6+ Years for experience
- Proficient in IP level ASIC verification
- Proficient in debugging firmware and RTL code using simulation tools
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Experience with power-aware verification methodologies and UPF
- Graphics pipeline knowledge
- Developing UVM based verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment.
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Strong background in the C++ language, preferably on Linux with exposure to Windows platform
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Good working knowledge of SystemC and TLM with some related experience.
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
- Desirable assets with prior exposure to video codec system or other multimedia solutions.
