MIPI Design Verification (DV) Engineer
Lead: (8 - 12 Yrs)
Engineers: (5+ yrs)
We are looking for an experienced MIPI Design Verification (DV) Engineer with strong expertise in MIPI Protocols (CSI/DSI/UniPro/CPHY/DPHY) to join our advanced design and verification team. The role involves working on complex SoC/IP verification for next-generation products.
MIPI Design Verification Engineers, focusing on complex IP/SoC verification using UVM/SystemVerilog, scripting (Python/Perl), and deep knowledge of bus protocols (AXI/AHB) and MIPI standards, often for high-speed interconnects (HSIO) like PCIe/USB/UFS, leveraging industry-standard ASIC tools for simulation and debugging. Roles range from engineers to leads/managers, emphasizing technical leadership, pre-silicon emulation, and strong communication for platform-level testing, with opportunities in multimedia/video codec verification as well.
Key Responsibilities & Skills (MIPI/HSIO focus):
- Verification Expertise: UVM, SystemVerilog, OOP, C-DPI.
- Protocols: Deep understanding of MIPI (D-PHY, C-PHY, etc.), AXI, AHB, USB, PCIe, UFS.
- Tools: Simulators, debuggers, linting tools, power-aware simulation.
- Scripting: Python, Perl, Ruby, Makefiles for automation.
- Domain: High-Speed I/O (HSIO) architecture, data transfer, compliance testing, pre-silicon emulation.
- Leadership: Technical leadership, platform-level test plan development for advanced roles.
Required Experience:
- 812 years of design verification experience.
- Strong hands-on expertise with MIPI protocols at least one of the following:
- MIPI CSI
- MIPI DSI
- MIPI C-PHY / D-PHY
- MIPI UniPro
- Proven experience in SystemVerilog, UVM based verification, constrained-random verification and testbench development
- Solid understanding of System Verilog assertion and coverage driven methodologies.
- Familiarity with Simulation tools Strong debugging complex SoC environment using tools like VCS, Questa, Incisive/Xcelium.
- Experience working on IP/Sub-system/SoC-level verification environments.
- Good understanding of digital design fundamentals, RTL, and SoC architectures.
- Experience with coverage metrics (functional/code coverage) and closure methodologies.
- Strong communication skills and ability to work in cross-functional teams.
