Memory Layout Engineer
Memory Layout Engineer
smartsoc solutions pvt ltd- Posted a month ago
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Job Description
We're Hiring | Memory Layout Engineers
We're looking for experienced Memory Layout Engineers to join our team and work on cutting-edge semiconductor technologies.
Experience: 4+ Years
Location: Bangalore
Key Responsibilities:
- Design memory layouts for various building blocks, including:
- Bit Cell Arrays ,Row Decoders, Column Decoders, Sense Amplifiers, Input/Output (I/O) Blocks
- Integrate top-level memory layouts.
- Perform physical verification using DRC and LVS.
- Ensure layouts comply with Design for Manufacturability (DFM) and Design for Yield (DFY) requirements.
- Analyze layouts for power integrity and signal integrity.
- Develop and maintain automation scripts using PERL, Shell, TCL, or SKILL.
Required Skills:
Strong hands-on experience in Memory Layout for advanced technology nodes.
Expertise in TSMC and/or other process technologies with lower nodes (2nm/3nm/5nm).
Solid understanding of physical verification, layout methodologies, and semiconductor design flows.
Scripting knowledge is an added advantage.
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Key Skills
About Company
Skills:
Shell, PERL, Tcl, Assura, Skill, Memory layout design, Cadence Virtuoso
Skills:
shielding , routing, guard rings, Custom Layout, LVS, Memory Layout, Calibre, CMOS devices matching techniques, advanced technology nodes, common-centroid layout, ERC, DRC, Cadence Virtuoso
Skills:
shielding , matching , Performance, parasitic effects, PEX, Cadence Virtuoso Custom Layout, 5nm FinFET, FinFET layout techniques, LVS, memory custom layout, design-rule requirements, SRAM bitcell memory arrays, layout optimization, ERC, DRC, sensitive-net routing, Calibre PVS, advanced-node tapeout, parasitics, guard rings, area density matching, symmetry, EM, Ir, layout-dependent effects
Skills:
matching , Routing, Parasitics, Memory Array Layout, Sram, LVS, NVM, Physical Verification, Calibre, floorplanning, Layout Optimization, Custom Layout, Memory Layout, Cadence Virtuoso, Placement, ERC, Hierarchical Layout, DRC, FinFET Technology, PPA Optimization, Memory Compiler, Rom
Memory Layout Engineer | Bangalore | 5-10 Years Experience | Immediate to 15 day Notice period onlyheadway tek inc
Skills:
physical closure, Synopsys, top-level memory integration, decoders, memory compiler IPs, bit-cell arrays, Sram, LVS, collaboration with circuit design, layout experience, sense amplifiers, power performance, yield manufacturability, verification PDK methodology teams, Cadence, optimize layouts for area, IR EM challenges, density verification, FinFET design rules, DFM guidelines, memory periphery, DRAM, DRC, layout and physical verification tools