PERL, Skill, Cadence LVS, Boundary conditions, LVS, memory architectures, ERC, Cadence Virtuoso layout editor, optimized layout design, DRC, Calibre physical verification flow, Finfet technology, layout design and verification tools

fast simulation tools and waveform viewers, deep submicron technology challenges, NMDL and CCST libraries, writing SPICE decks stimulus and test vectors, FinFET technology, layout impact on speed capacitance power and area, generating libraries and performing QA sign-off, layout parasitic extraction, memory architectures and performance optimization, LVS DRC debugging skills and verification for lower technology nodes, memory leafcell layout design, EDA tools including Cadence SKILL scripting and automation for compiler flows and layout reuse