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Job Title: Memory Layout Engineer
Location: Bangalore
Job Type: Full-Time
Experience: 4-10 Years
Educational Qualification:
Required Skills & Experience:
Note:
1. Applications will only be accepted through the ATS link provided above. Profiles shared through other means will not be considered.
2. We do not charge any fee from candidates at any stage. If anyone approaches you for money in exchange for this opportunity, treat it as fraud and report it to us immediately.
Job ID: 147236611
Skills:
PERL, Skill, Cadence LVS, Boundary conditions, LVS, memory architectures, ERC, Cadence Virtuoso layout editor, optimized layout design, DRC, Calibre physical verification flow, Finfet technology, layout design and verification tools
Skills:
fast simulation tools and waveform viewers, deep submicron technology challenges, NMDL and CCST libraries, writing SPICE decks stimulus and test vectors, FinFET technology, layout impact on speed capacitance power and area, generating libraries and performing QA sign-off, layout parasitic extraction, memory architectures and performance optimization, LVS DRC debugging skills and verification for lower technology nodes, memory leafcell layout design, EDA tools including Cadence SKILL scripting and automation for compiler flows and layout reuse
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