MemoryLayout3+ Years
JobDescription
- Experience inlayoutdesign of leaf cell level and top level (integration) of custom memories example SRAM and Register Files
- Work closely with circuit designers to understand schematics and translate them into optimizedlayouts.
- Good understanding of Floor-planning, placement, matching, routing, parasitics andlayoutconstraints.
- Good understanding and debugging of physical verification checks DRC, LVS, ERC and reliability check EM and IR.
- Good understanding of advanced process nodes 5nm and below.
- Preferable with scripting experience in SKILL, Python, or TCL.
Required Skill Set
- Experience in Custom based memories OR compiler-based memories
- Exposure to high-performance and/or low-powermemorylayoutoptimization techniques.
Experience in Years
- Minimum of 3 plus years of experience inmemorylayoutdesign
If the opportunity aligns with your career goals or if you'd like to learn more, I'd be happy to connect.
