Manager - Design Engineering

About Tessolve

Tessolve offers end-to-end semiconductor engineering solutions from design, test, and product engineering to embedded systems and full turnkey solutions. With a strong global presence and deep expertise across domains, we help customers accelerate innovation and time-to-market.

Role Overview

We are seeking an experienced Physical Design (PD) Manager to lead our PD team in Bangalore. The ideal candidate will have strong hands-on expertise in all aspects of ASIC Physical Design and proven leadership experience managing projects, teams, and customer engagements.

You will be responsible for driving project execution, ensuring quality deliverables, and mentoring engineers to achieve excellence in PD flow implementation.

Key Responsibilities

• Roles:
  
  

We are seeking a highly experienced Senior Synthesis & Static Timing Analysis (STA) Engineer with strong hands-on expertise in both Synopsys and Cadence tool flows. The ideal candidate will own the RTL-to-netlist implementation flow, perform timing closure across multiple modes and corners, and collaborate with cross-functional teams to achieve sign-off quality results for complex SoC/ASIC designs.

Responsibilities

• Perform RTL synthesis using Synopsys Design Compiler and/or Cadence Genus, including constraint management, optimization for PPA (Power, Performance, Area), and timing convergence.
• Develop and maintain timing constraints (SDC) for hierarchical and flat synthesis and STA.
• Execute Static Timing Analysis (STA) at block and top level using Synopsys PrimeTime and/or Cadence Tempus, covering setup, hold, clock gating, and path-based analysis.
• Analyze and debug timing violations, transition/capacitance issues, and perform necessary timing ECOs.
• Support multi-mode, multi-corner (MMMC) timing sign-off across various operating conditions.
• Work closely with RTL design, Physical Design, and DFT teams to achieve complete timing closure and clean sign-off.
• Ensure LEC (Logical Equivalence Check) between RTL, synthesized netlists, and post-layout netlists using Conformal or Formality.
• Support and automate ECO flows and timing closure scripts using TCL/Python/Perl.
• Drive flow improvements and methodology enhancements across synthesis and STA stages.
• Collaborate with PD teams for timing-driven placement, CTS, and route guidance.
  
  

Education: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering.

• Experience: 9+ years of experience in ASIC/SoC design, focusing on Synthesis & STA.
• Tool Proficiency:
  
  

oSynthesis: Synopsys Design Compiler, Cadence Genus

oSTA: Synopsys PrimeTime, Cadence Tempus

oLEC: Synopsys Formality, Cadence Conformal

oScripting: TCL, Perl, Python, Shell

• Strong knowledge in:
  
  

oSDC constraints, timing exceptions, and path analysis

oOCV, AOCV, POCV, CRPR handling in MCMM environments

oLow power synthesis and UPF/CPF flow integration

oHierarchical and top-level STA sign-off methodologies

Preferred Skills

• Experience with advanced process nodes (7nm / 5nm / 3nm).
• Deep understanding of timing-driven physical design interaction.
• Hands-on experience in timing ECO automation and custom script development.
• Familiarity with clock architecture, multi-voltage, and multi-frequency designs.
• Exposure to timing correlation between synthesis, P&R, and sign-off tools.
  
  

Soft Skills

• Strong analytical, problem-solving, and debugging capabilities.
• Excellent teamwork and communication across global, cross-functional teams.
• Self-driven and proactive in driving design closure and flow improvements.
  
  

Nice to Have

• Experience with EDA tool qualification and benchmarking.
• Contribution to flow development or CAD automation frameworks.
• Familiarity with AI/ML-driven optimization in synthesis or STA.