We are seeking a highly skilled Low Power Formal Verification Engineer to join our team. The ideal candidate will possess deep expertise in low power formal verification, advanced constraint development, and a strong understanding of timing analysis in complex SoC designs. This role is critical for ensuring the power efficiency and functional correctness of our designs through rigorous verification methodologies.
Roles and Responsibilities:
- Utilize work experience in Advanced Constraint Verification & post-layout STA (Static Timing Analysis).
- Apply expertise in Low Power Formal Verification techniques to ensure power efficiency and functional correctness.
- Demonstrate expertise in Constraint Development for both Functional and DFT (Design For Testability) aspects.
- Possess knowledge of IP constraints on interfaces like DDR3/4, Multiprotocol SerDes, ARM core and Subsystem, USB3.0, which is a significant plus.
- Apply expertise in MCMM (Multi-Corner Multi-Mode) definitions for comprehensive timing analysis.
- Possess knowledge in Abstraction definition and creation (e.g., ETM/ILM/Hyperscale).
- Understand Extraction & PTSI (Power Timing Static Interconnect) pruning parameter definitions.
- Define FILL aware timing strategies/flow.
- Develop DMSA (Design for Manufacturing and System-level Analysis) and ECO (Engineering Change Order) strategy definitions.
- Conduct Clock Scaling Analysis to ensure robust design operation across different clock frequencies.
Required Skills and Qualifications:
- Expertise in Low Power Formal Verification.
- Strong background in Constraint Development (Functional, DFT).
- Proficiency in advanced constraint verification and post-layout STA.
- Knowledge of IP constraints (DDR3/4, Multi-protocol SerDes, ARM core, USB3.0) is highly beneficial.
- Expertise in MCMM definitions.
- Understanding of abstraction definition and creation (ETM/ILM/Hyperscale).
- Knowledge of extraction & PTSI pruning parameter definitions.
- Experience with FILL aware timing strategies/flow definition.
- Familiarity with DMSA and ECO strategy definitions.
- Ability to perform Clock Scaling Analysis.
