Lead STA Engineer

WE ARE HIRING | Static Timing Analysis (STA) Roles at ACL Digital!

Are you passionate about tackling timing challenges on complex, advanced-node SoCs ACL Digital is expanding its VLSI team across Bangalore, Hyderabad, and Chennai!

We are looking for hands-on, high-performing VLSI professionals to join our timing closure team:

Open Roles:

1⃣ Full-Chip SoC Timing Lead (8–10+ Yrs)

2⃣ STA Senior Engineers (6–8 Yrs)

Locations: Bangalore / Hyderabad / Chennai

Notice Period: Immediate to 30 Days (Preferred)

Experience: 4 to 10+ Years

Key Responsibilities (Lead Role):

• Full-Chip Timing Closure: Own and drive timing signoff for complex SoCs across all modes and corners from synthesis through PnR to tapeout.

• STA & Analysis: Execute setup, hold, recovery/removal, clock gating, and async path analysis.

• Advanced Effects: Resolve issues related to cross-talk, noise, OCV/AOCV/POCV, derates, and variation effects in 7nm / 5nm / 3nm nodes.

• ECO Closure: Lead timing ECO strategies for minimal PPA impact.

• Methodology & Quality: Drive implementation vs. signoff correlation, enforce best practices, and mentor junior/mid-level STA engineers.

Key Requirements:

• B.E/B.Tech/M.E/M.Tech in ECE / Electrical / VLSI / Microelectronics.

• Hands-on expertise with industry-standard STA and signoff tools (PrimeTime, Tempus, QRC, etc.). • Proven track record on advanced finFET nodes.

How to Apply: If you are ready to scale up your career with cutting-edge SoC projects, send your updated resume to [Confidential Information] or drop a DM directly!