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We're Hiring at ACL Digital!
Position: Lead Physical Design engineer
Experience: 8 to 10 Years
Location: Bangalore
Notice Period: Immediate to 30 Days
Job Description – Physical Design Engineer
Role Overview:
We are looking for a highly skilled Lead Physical Design Engineer with hands-on experience in high-frequency SoC designs, specifically in DDR and advanced node technologies. The ideal candidate will be responsible for the complete RTL to GDSII implementation flow.
Key Responsibilities:
Key Skills Required:
This is your chance to be part of innovative semiconductor product development with a talented team at ACL Digital. If you meet the above requirements and are looking for your next challenge — we'd love to connect!
Send your resume to: [Confidential Information]
Job ID: 126907863
Skills:
redhawk , Scripting Languages, Python, Perl, Tcl, power analysis, primetime, PrimeClouser, Tempus, Cadence Innovus, manufacturing sign-off, DFT insertion, Voltus, ASIC SoC physical design, Calibre, EDA Tools, low-power design, EM IR analysis, advanced nodes, multi-clock domain handling, Timing Analysis, Physical Verification, reliability checks, Signal Integrity
Skills:
Scripting, Static Timing Analysis, Routing, Design Compiler, primetime, ICC2, Synopsys Fusion Compiler, LVS, Cadence Genus, Innovus, Physical Verification, Extraction, Formal Equivalence, StarRC, Placement, Floor-plan Physical Implementation, RTL to GDS2 flow, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Physical Design, Timing Closure, DRC, PNR tools
Skills:
Tcl Scripting, Static timing Analysis, Cadence Tools, Synthesis, Physical Design, Physical Verification, Backend flows, Clock Tree Synthesis, Place Route Reliability
Skills:
redhawk , Apache, Tcl, Perl, Routing, Python, EM, CPU physical design, Place And Route, Placement, Ir, Calibre, PPA tradeoffs, Synthesis, DRC, Extraction, Cadence PrimeTime, floor plan synthesis, LVS, Physical Verification, CTS, signoff, Synopsys Fusion Compiler, floor-planning, physical design methodologies, Timing Closure, StarRC
Skills:
clock distribution , Tcl, Clp, PERL, Gds, Synthesis, IP integration, Power and Signal Integrity Analysis, Physical Design, Clock Tree Synthesis, ERC, DRC, PNR, Tape Out, Extraction, upf, Dfm, Timing Closure, low power design, LVS, Physical Verification, cpf, Floorplan, Sta, PERC, Tk, LEC flow
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