Lead Physical Design Engineer

Physical Design Engineer

Location: Bengaluru, India

Experience: 6+ years

About the Role

We are seeking an experienced Lead Physical Design Engineer with strong expertise in Cadence Innovus and EMIR analysis to join our VLSI design team in Bengaluru. The ideal candidate will have hands-on experience driving the full RTL-to-GDSII flow and ensuring robust chip-level power, performance, and area (PPA) optimization.

Key Responsibilities

• Execute full-chip and block-level physical design using Cadence Innovus, from floorplanning to GDSII.
• Perform timing closure, power optimization, and signal integrity analysis at advanced technology nodes.
• Conduct EM/IR (EMIR) analysis and sign-off to ensure robust power delivery and reliability.
• Collaborate closely with RTL, synthesis, verification, and DFT teams to meet design targets for performance and manufacturability.
• Manage design constraints, parasitic extractions, and timing ECOs across multiple iterations.
• Contribute to physical verification (DRC/LVS) and work with foundry teams for sign-off.
• Provide mentorship and technical guidance to junior PD engineers.

Required Skills & Experience

• Bachelor's or Master's degree in Electronics / Electrical / VLSI Engineering or related field.
• Minimum 6 years of hands-on experience in physical design and sign-off.
• Strong expertise in Cadence Innovus implementation flow and scripting (TCL/Perl/Python).
• In-depth knowledge of EMIR analysis and sign-off methodologies (Voltus, RedHawk, or equivalent).
• Solid understanding of STA, floorplanning, clock tree synthesis (CTS), and routing optimization.
• Experience with technology nodes at 16nm or below preferred.
• Excellent problem-solving, debugging, and cross-functional communication skills.

Good to Have

• Exposure to Power/IR design optimization at system level.
• Familiarity with multi-voltage domain design and UPF flows.
• Experience with scripting automation for layout or timing processes.

Would you like this job description to be tailored for an EDA service company or an in-house semiconductor design team (e.g., product company) This will help fine-tune the tone and emphasis.

About Us:

Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we're committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.

Website

https://www.siliconpatterns.com