Lead Physical Design Engineer

Lead Physical Design Engineer

Location: Bengaluru

Experience: 6+ Years

About the Team

Our silicon engineering team builds high-performance, power-efficient chips that power next-generation computing platforms at massive scale. We work across the full stack of hardware innovation — from architecture to silicon implementation — solving complex engineering challenges that impact millions of users globally.

We are looking for a Lead Physical Design Engineer to drive implementation and signoff of advanced SoCs in cutting-edge technology nodes. You will work closely with world-class architects, RTL designers, STA, DFT, CAD, and package teams to deliver best-in-class silicon.

What You'll Do

• Lead end-to-end physical design implementation for complex SoC/IP blocks from RTL handoff to tapeout.
• Drive PPA optimization across floorplanning, placement, CTS, routing, and timing closure.
• Own physical signoff including STA, IR/EM, signal integrity, DRC/LVS, and reliability closure.
• Collaborate with architecture, RTL, power, and verification teams to influence design decisions early in the development cycle.
• Develop scalable methodologies and automation to improve design productivity and quality.
• Debug and resolve complex design convergence issues in advanced process technologies.
• Mentor engineers across the team and help raise the technical bar through reviews and best practices.
• Partner with CAD and foundry teams to enable next-generation implementation flows.
• Drive execution with a strong focus on quality, schedule, and silicon success.

Minimum Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or related field.
• 6+ years of industry experience in ASIC/SoC Physical Design.
• Strong expertise in:
• Floorplanning and power planning
• Placement, CTS, routing, and timing closure
• Physical verification and signoff methodologies
• Multi-voltage and low-power design implementation
• Deep understanding of:
• STA and MMMC methodologies
• Signal integrity, IR drop, EM analysis
• Advanced node implementation challenges (16nm/7nm/5nm or below)
• Hands-on experience with industry-standard EDA tools such as:
• Cadence Innovus
• Synopsys ICC2
• PrimeTime/Tempus
• Voltus/RedHawk
• Strong scripting and automation skills in Tcl, Python, or Perl.
• Proven ability to independently drive complex technical projects to completion.

Preferred Qualifications

• Experience with full-chip integration and hierarchical SoC implementation.
• Multiple successful tapeouts in advanced technology nodes.
• Experience building scalable PD methodologies or automation frameworks.
• Strong understanding of power-performance-area tradeoffs in high-performance compute designs.
• Experience working in high-volume consumer silicon or datacenter-class products.

What Sets You Apart

• You thrive in ambiguous, fast-moving environments.
• You balance deep technical expertise with execution excellence.
• You raise engineering standards through leadership, mentorship, and innovation.
• You are passionate about building silicon that scales globally.

Why Join Us

• Work on industry-leading silicon programs at massive scale.
• Collaborate with some of the best minds in hardware engineering.
• Solve technically challenging problems in advanced process technologies.
• Competitive compensation, benefits, and long-term career growth opportunities.

About Us:

LeadSoC Technologies offers cutting edge Engineering Design services in VLSI and Embedded Systems. We have been growing rapidly over the last 9+ years to meet the evolving needs of the Semiconductor, Automotive, Telecom and Consumer Electronics segments. Our End-to-End VLSI design services span Micro Architecture to Tape Out and beyond with Post Silicon support. We have been involved in co-development of multiple SOC releases for our clients. LeadSoC has in house VLSI labs equipped with state of art tools (from leading EDA OEM's) for grooming talent. We work on SOC's, FPGA and ASIC platforms in areas spanning Digital Front End Design & Verification, Back End Design (RTL=> GDS), Analog & Custom Design & Verification. We also work on RF & Board Design for OEMs. Our Software practice works in areas spanning Firmware design, Hardware Abstraction, Kernel Space & User space design. We work on both bare metal and RTOS/Linux like platforms across x86, ARM, MIPS & Power PC architectures across multiple chipsets. Our presence in Concept to Manufacturing, spans across a broad spectrum of capabilities including Board Design, Platform Software solutions (Boot Loader, Bare Metal Firmware, Drivers/BSP, Abstraction layers), Middleware (Stacks, Frameworks, diagnostics), Target application, HMI (industry standard frameworks), IoT and Cloud (AWS, GCP, Azure) applications and V&V services. We have an embedded Software COE with in-house Labs, powered by open-source tool chain equipped with variety of reference boards. This environment enables our engineers to play while they learn. It also creates an environment for the engineers to ideate / create reference Solutions, POC designs. Our teams have been involved in providing frameworks for On-board Diagnostics, Manufacturing diagnostics, Post & Pre-Silicon Validation and Performance Optimization for products based on Linux / RTOS platforms. We have also worked on migrating stacks from legacy to NextGen platforms.

Website

http://www.leadsoc.com